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SPT7935
12-BIT, 20 MSPS, 79 mW A/D CONVERTER
FEATURES
* * * * * * * 12-Bit, 20 MSPS Analog-to-Digital Converter Monolithic CMOS Internal Track-and-Hold Low Input Capacitance: 1.4 pF Low Power Dissipation: 79 mW 2.8 - 3.6 V Power Supply Range TTL-Compatible Outputs
APPLICATIONS
* * * * * * * CCD Imaging Cameras and Sensors Medical Imaging RF Communications Document and Film Scanners Electro-Optics Transient Signal Analysis Handheld Equipment
GENERAL DESCRIPTION
The SPT7935 12-bit, 20 MSPS analog-to-digital converter has a pipelined converter architecture built in a CMOS process. It delivers high performance with a typical power dissipation of only 79 mW. With low distortion and high dynamic range, this device offers the performance needed
for imaging, multimedia, telecommunications and instrumentation applications. The SPT7935 is available in a 44-lead Thin Quad Flat Pack (TQFP) package in the industrial temperature range (-40 to +85 C).
BLOCK DIAGRAM
ADC
DAC
+
- G=2
D<1...0> Pipeline Stage
VIN+ VIN- VREF+ VREF- CLK Clock Driver Digital Delays, Error Correction and Output 12 Stage 1 Stage 2 Stage 9 Stage 10 2-Bit ADC
Digital Output (D0 - D11)
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VDD1 .................................................................... -0.5 V to +6 V VDD2 .................................................................... -0.5 V to +6 V VDD3 .................................................................... -0.5 V to +6 V Input Voltages Analog Input ................................. -0.5 V to (VDD +0.5 V) Digital Input .................................. -0.5 V to (VDD +0.5 V) VREF+ .......................................... -0.5 V to (VDD +0.5 V) VREF- .......................................... -0.5 V to (VDD +0.5 V) CLK .............................................. -0.5 V to (VDD +0.5 V) Temperature Operating Temperature ............................. -40 to +85 C Storage Temperature ............................... -65 to +125 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN-TMAX , VDD1=VDD2=VDD3=3.3 V, VREF-=1.0 V, VREF+=2.0 V, Common Mode Voltage=1.65 V, CLK=20 MSPS, Bias 1=90 A, Bias 2=9.5 A, Differential Input, Duty Cycle=50%, unless otherwise specified. PARAMETERS DC Accuracy Resolution Differential Linearity Integral Linearity No Missing Codes Analog Input Input Voltage Range (Differential) Common Mode Input Voltage Input Capacitance Input Bandwidth (Large Signal) Offset (Mid-scale) Gain Error Reference Voltages Reference Input Voltage Range (VREF+ - VREF-) Negative Reference Voltage (VREF-) Positive Reference Voltage (VREF+) Common Mode Output Voltage (VCM) VREF+ Current VREF- Current Switching Performance Maximum Conversion Rate Pipeline Delay (See Timing Diagram) Aperture Delay Time (TAP) Aperture Jitter Time Dynamic Performance Effective Number of Bits IN = 5.0 MHz IN = 10.0 MHz Signal-To-Noise Ratio IN = 5.0 MHz IN = 10.0 MHz Total Harmonic Distortion IN = 5.0 MHz IN = 10.0 MHz TEST CONDITIONS TEST LEVEL MIN SPT7935 TYP 12 0.6 3.0 Guaranteed 0.6 1.2 1.0 1.65 1.4 120 1.0 0.3 1.0 1.0 2.0 1.65 35 -25 1.7 1.9 MAX UNITS Bits LSB LSB
V V VI IV IV V V V V IV IV IV VI V V VI IV V V
VIN+=VIN-=VCM
V V pF MHz % FSR % FSR V V V V A A MHz Clocks ns ps-rms
0.6 0.9 1.9 1.3
1.7 1.3 2.6 1.8
IO = -1 A
20 7.5 5 10
VI V VI V VI V
9.2
9.8 9.0 62 58 -68 -60 -61
Bits Bits dB dB dB dB
59
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ELECTRICAL SPECIFICATIONS
TA=TMIN-TMAX , VDD1=VDD2=VDD3=3.3 V, VREF-=1.0 V, VREF+=2.0 V, Common Mode Voltage=1.65 V, CLK=20 MSPS, Bias 1=90 A, Bias 2=9.5 A, Differential Input, Duty Cycle=50%, unless otherwise specified. PARAMETERS Dynamic Performance-Continued Signal-To-Noise and Distortion IN = 5 MHz IN = 10 MHz Spurious Free Dynamic Range IN = 5.0 MHz IN = 10.0 MHz Differential Phase Differential Gain Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) Power Supply Requirements Supply Voltages VDD1, VDD2, VDD3 Supply Current IDD Power Dissipation Power Supply Rejection Ratio (PSRR) TEST CONDITIONS TEST LEVEL MIN SPT7935 TYP MAX UNITS
VI V VI V V V VI VI VI VI V VI VI IV
57
61 56 70 61 0.2 0.5
dB dB dB dB Degrees %
62
80% VDD 20% VDD 1 A 1 A pF V V ns
VIN = GND VIN = VDD
1.8 85% VDD 4 95% VDD 0.1 8
IO = -2 mA IO = +2 mA
0.4 12
IV VI VI V
2.8
3.3 24 79 67
3.6 30 100
V mA mW dB
TEST LEVEL I All electrical characteristics are subject to the following conditions: All parameters having II min/max specifications are guaranteed. The Test Level column indicates the specific III device testing actually performed during proIV duction and Quality Assurance inspection. Any blank section in the data column indiV cates that the specification is not tested at the specified condition. VI
TEST LEVEL CODES
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Input Frequency
80
THD, SNR, SINAD vs Sample Rate
80
70
70
THD SNR
THD SNR SINAD
THD, SNR, SINAD (dB)
THD, SNR, SINAD (dB)
60
THD SNR SINAD
60 SINAD 50
50
40
40
30
30
20 100
20
Input Frequency (MHz)
101
102
10 0
101
102
Sample Rate (MSPS)
Note: Bias1 and Bias2 currents optimized for each sample rate.
THD, SNR, SINAD vs Temperature
70
Power Dissipation vs Sample Rate
150
68
125
THD, SNR, SINAD (dB)
THD
66
Power Dissipation (mW)
100
64
SNR
62
75
SINAD
60
50
58
25
56 0 25 70
0
Temperature (C)
10 0
101
102
Sample Rate (MSPS)
Note: Bias1 and Bias2 optimized for each sample rate.
Bias 1 Voltage vs Bias 1 Current
3.4 3.2 3.0 0.90
Bias 2 Voltage vs Bias 2 Current
0.85
VBias1 (V)
0.80
VBias2 (V)
2.8 2.6 2.4 2.2 2.0 0 30 60 90 120 150 180
IBias1 VBias1 30 2.19 60 2.53 90 2.79 120 3.00 150 3.22
0.75
0.70
IBias2 3 6 9 12 15
VBias2 0.6975 0.7535 0.796 0.8295 0.8595
0.65
0.60 0 3 6 9 12 15 18
IBias1 (A)
IBias2 (A)
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Figure 1 - Timing Diagram
Sampling Points N-1 N N+1
tAP AIN CLK
N+2
N+6
N+7
N+8
tD DOUT
N-2 N-1 N
GENERAL DESCRIPTION
The SPT7935 is an ultra-low power, 12-bit, 20 MSPS ADC. It has a pipelined architecture and incorporates digital error correction of the 11 most significant bits. This error correction ensures good linearity performance for input frequencies up to Nyquist. The inputs are fully differential, making the device insensitive to system-level noise. This device can also be used in a single-ended mode. (See analog input section.) With the power dissipation roughly proportional to the sampling rate, this device is ideal for very low power applications in the range of 1 to 20 MSPS.
TYPICAL INTERFACE CIRCUIT
The SPT7935 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7935 in normal circuit operation. The following sections provide a description of the functions and outline critical performance criteria to consider for achieving the optimal device performance.
ANALOG INPUT
The input of the SPT7935 can be configured in various ways depending on if a single-ended or differential, AC- or DCcoupled input is desired.
+3.3 V CLK In
(3 V Logic)
Figure 2 - Typical Interface Circuit
Ref- In
(+1.15 V)
4.7 F +
.01 F
10 F +
+3.3 V
.01 F
Ref+ In
(+2.15 V) + 4.7 F .01 F 11
+3.3 V Digital
0.1 F 1
GND CLK
Decoupling Cap
VREF-
VDD1
VDD2
N/C
VDD2
VDD1
VDD3
VREF+
VDD1
12
N/C N/C N/C
VDD3 44 (LSB) D0 D1 D2
90 A 9.5 A .01 F (+1.65 V)
GND Bias1 Bias2 VCM GND
U1 SPT7935
D3 D4 D5 D6 D7 D8 D9
D10 D11
Interfacing 3 V Logic
RF In
51
68 pF
VIN+ VIN-
22 Minicircuit T1-6T
GND
GND
34 (MSB)
23
33
AGND Notes: All VDD1, VDD2 and VDD3 should be tied together. FB = Ferrite Bead; must be placed as close to U1 as possible.
FB
DGND
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The AC coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. The center tap is connected to the VCM pin as shown in figure 2. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the inputs attenuates kickback noise from the internal sample and hold. Figure 3 illustrates a solution (based on operational amplifiers) that can be used if a DC coupled single-ended input is desired. The selection criteria of the buffer op-amps is as follows: - Open loop gain >75 dB - Gain bandwidth product >50 MHz - Total harmonic distortion -75 dB - Signal to noise ratio >75 dB
COMMON MODE VOLTAGE REFERENCE CIRCUIT
The SPT7935 has an on-board common mode voltage reference circuit (VCM). It is typically one-half of the supply voltage and can drive loads of up to 20 A. This circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit.
BIAS CURRENT CIRCUITS
The bias currents suggested (Bias 1 and Bias 2 in figure 2) optimize device performance for the stated sample rate of 20 MSPS. To achieve the best dynamic performance when operating the device at sample rates other than 20 MSPS, the bias current levels should be adjusted. Table I shows the settings for Bias 1 and Bias 2 for selected sample rates. The "Bias Voltage vs Bias Current" graphs on page 4 show the relationship between the bias current and the bias voltage. Table I - Sample Rate Settings Sample Rate (MHz) 1 5 10 20 Bias 1 (A) 20 50 80 90 Bias 2 (A) 3.5 6.5 8.0 9.5
POWER SUPPLIES AND GROUNDING
The SPT7935 is operated from a single power supply in the range of 2.8 to 3.6 volts. Nominal operation is suggested to be 3.3 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible.
REFERENCES
The SPT7935 has a differential analog input. The voltages applied to the VREF+ and VREF- pins determine the input voltage range and are equal to (VREF+ - VREF-). This voltage range will be symmetric about the common mode voltage. Externally generated reference voltages must be connected to these pins. (See figure 2, Typical Interface Circuit.) For best performance, these voltages should be symmetrical about the midpoint of the supply voltage.
Figure 3 - DC-Coupled Single Ended to Differential Conversion (Power Supplies and Bypassing are Not Shown)
R3 VCM (R3)/2 - + Input Voltage (0.5 V) R2 R2 R - + 15 pF VIN- 51 R R 51 VIN+ R3
R ADC
+ - R
51
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CLOCK
The SPT7935 accepts a low voltage CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non-50% duty cycle reduces the settling time available for every other stage and thus potentially causing a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 2 ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and standard transmission line practices be followed.
DIGITAL OUTPUTS
The digital output data appears in an offset binary code at 3.3 V CMOS logic levels. A negative full scale input results in an all zeros output code (000...0). A positive full scale input results in an all 1's code (111...1). The output data is available 7.5 clock cycles after the data is sampled. The input signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up.
EVALUATION BOARD
The EB7935 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7935. The board includes an on-board clock driver, adjustable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7935) is also available which describes the operation of the evaluation board and provides an example of the recommended power and ground layout and signal routing. Contact the factory for price and availability.
PACKAGE OUTLINE
44L TQFP
A B
INCHES SYMBOL A B C D E F
C D
MILLIMETERS MAX MIN 12.00 Typ 10.00 Typ 10.00 Typ 12.00 Typ 0.80 Typ 0.018 0.057 0.006 0.030 0.300 1.35 0.05 0.450 1.00 Typ 0-7 0.45 1.45 0.15 0.750 MAX
MIN 0.472 Typ 0.394 Typ 0.394 Typ 0.472 Typ 0.031 Typ 0.012 0.053 0.002 0.018 0.039 Typ 0-7
G H I J K
Index
Pin 1
E
F
G I H J K
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PIN ASSIGNMENTS
D0 (LSB) 43 VDD3 44 D6 D8 D1 42 D3 40 D4 D7 D9 D2 41 D5 38
PIN FUNCTIONS
Name VIN+, VIN- VREF+, VREF-
33 32 31 30 29 28 27 26 25 24 23 D10 D11 (MSB) GND GND GND GND GND GND GND GND GND
Function Analog Inputs External Reference Inputs Input Clock Common Mode Output Voltage (1.65 V typ) Bias Current (90 A typ) Bias Current (9.5 A typ) Digital Outputs (D0 = LSB) Analog Ground Analog Power Supply Digital Power Supply Digital Output Power Supply No Connect Pins. Recommended to connect to analog ground.
37
36
39
35
34
GND CLK N/C VDD3 VDD2 VDD2 VDD1 VDD1 VDD1 VREFVREF+
1 2 3 4 5 6 7 8 9 10 11 15 14 16 17 18 19 12 N/C 13 N/C 20 21 22
CLK VCM Bias 1 Bias 2 D0 - D11 GND VDD1 VDD2 VDD3 N/C
GND
GND
ORDERING INFORMATION
PART NUMBER SPT7935SIT TEMPERATURE RANGE -40 to +85 C PACKAGE TYPE 44L TQFP
N/C
N/C
VIN-
Bias 1
Bias 2
VIN+
VCM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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